Honored Contributor
Honored ContributorThanks for replying.
--- Quote Start --- Have you tried booting your PC with this type of configuration? --- Quote End --- Yes. One of our Xeon boxes has a BIOS that lets your place your PCIe resources above the 4GB mark and allows up to a total of 1 TB of PCIe space. "lspci" under Linux even shows that the BAR size of the dev. board is 4 GB as does the sysfs entry. The really frustrating thing is that, occasionally, with some builds I can actually get it to work and access all 4 GB of the BAR. (I can tell because the design has instrumentation that I can get to through BAR2.). My first thought was a timing problem, but looking carefully through the timing report doesn't show anything. --- Quote Start --- There is very rarely any need to have PCIe (or PCI) BARs bigger than a few kB or MB. --- Quote End --- Yes, I can probably use DMA to bypass the BAR mechanism completely. We are building a memory subsystem and this dev. board is being used more like an accelerator for simulations. I would prefer not to add extra logic and software between the design and the testbench. Using mmap() to make it appear like a chunk of memory seems more natural. Thanks, Chandan
