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I have a design using the PCIe compiler in Qsys with 2 BARs on a Stratix IV dev. kit. My aim was to have BAR0:1 address 4 GB of memory and BAR2 access the control/status registers (2 MB).
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Have you tried booting your PC with this type of configuration?
I'd say there's a 99% chance your PC will not even boot.
There is very rarely any need to have PCIe (or PCI) BARs bigger than a few kB or MB. If you want to transfer data between 4GB on the board and your host memory, then you would use DMA from the board, in which case the board is the bus master, and the BAR size is of no consequence (since that is used only by the host).
Cheers,
Dave
Honored Contributor
