Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

PCI-E hard IP in Qsys, external Interrupt connection

Hi All,

I am new to qsys tool....

I need to implement a system in Qsys using PCI-E bus.

System consist of PCI-E bus, 6 UART cores and other custom logics inside Altera FPGA interfacing with external host.PCI-E configured as End point only.

In Qsys I have added PCI hard IP, Avlon MM-slave translator, Clk component, Reset component and an Irq bridge.

There are 6 interrupts coming from 6 UARTs need to be passed to host through PCI-E using MSI mode. I am using UARTs from external vendors(not qsys components).

How these interrupt need to be connected to PCI-E? whether IRQ bridge is required? How I can connect UARTs interrupt to IRQ bridge?

How many IRQ bridges is required?

Thanks in advance..

zeal

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Hi All,

    pls see the attachment for better understanding of the problem...

    If I instantiate one IRQ bridge with 6 interrupt inputs, I am not able to set the priority(like 0,1,2,..) at the sender port connection.

    anybody faced similar issue??

    Rgds,

    zeal