Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

PCI-E hard IP in Qsys, external Interrupt connection

Hi All, I am new to qsys tool.... I need to implement a system in Qsys using PCI-E bus. System consist of PCI-E bus, 6 UART cores and other custom logics inside Altera FPGA interfacing with ex...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Hi All,

pls see the attachment for better understanding of the problem...

If I instantiate one IRQ bridge with 6 interrupt inputs, I am not able to set the priority(like 0,1,2,..) at the sender port connection.

anybody faced similar issue??

Rgds,

zeal