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Honored Contributor
Honored ContributorPassing array as a port via hw.tcl file
Hello, System Verilog supports using array as a port. We are creating our own component which uses System Verilog. That component is going to be used in Qsys. So, we will need to use hw.tcl fil...
Altera_ForumHonored Contributor
Honored ContributorHello,
Thank you for your reply. Yes, we can use the method which you have mentioned. Cheers, Bhaumik
