Forum Discussion
jeffshh056
New Contributor
New ContributorPassed "Design Analysis" stage but failed with "Analysis & Synthesis" stage
Hi There,
I am using Quartus 22.3/22.4 version to compile my design.
My design contains many folders and many source code, including *.svh files.
I am using quartus_sh to run a tcl file to ...
ShengN_altera
Super Contributor
Super ContributorHi Shu,
Check this link https://www.intel.com/content/www/us/en/docs/programmable/683463/22-4/verify-verilog-compilation-unit.html
Actually Quartus Pro Edition use Single-file compilation unit (SFCU) method to select compilation unit files which is better method compared to Multi-file compilation unit (MFCU) method.
I don't think that would be the root cause. It's better to check whether the module name match or not.
Thanks,
BRs,
Sheng
