Passed "Design Analysis" stage but failed with "Analysis & Synthesis" stage

Hi Shu,

Check this link https://www.intel.com/content/www/us/en/docs/programmable/683463/22-4/verify-verilog-compilation-unit.html

Actually Quartus Pro Edition use Single-file compilation unit (SFCU) method to select compilation unit files which is better method compared to Multi-file compilation unit (MFCU) method.

I don't think that would be the root cause. It's better to check whether the module name match or not.

Thanks,

BRs,

Sheng