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jeffshh056's avatar
jeffshh056
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3 years ago

Passed "Design Analysis" stage but failed with "Analysis & Synthesis" stage

Hi There, I am using Quartus 22.3/22.4 version to compile my design. My design contains many folders and many source code, including *.svh files. I am using quartus_sh to run a tcl file to ...
ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

Hi Shu,


I think that's not the problem of tcl script then. Check in the axi_bridge.sv, make sure the module name is the same matched name axi_bridge. Same goes for the rest of undefine entity.


Thanks,

Best regards,

Sheng


jeffshh056's avatar
jeffshh056
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3 years ago

One more observation, if I change to "MFCU" mode, the synth do starts!!!

set_global_assignment -name VERILOG_CU_MODE MFCU

Do you happen to know why it make such difference, does it have anything to do with AUTO-DISCOVERY?