Forum Discussion

jeffshh056's avatar
jeffshh056
Icon for New Contributor rankNew Contributor
2 years ago

Passed "Design Analysis" stage but failed with "Analysis & Synthesis" stage

Hi There, I am using Quartus 22.3/22.4 version to compile my design. My design contains many folders and many source code, including *.svh files. I am using quartus_sh to run a tcl file to ...
ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
2 years ago

Hi,


I don't think the compile file list order matter. In gui, may be you can go to Project -> Generate Tcl File for Project. Then in auto-generated tcl script add two lines below:

package require ::quartus::flow

...

execute_flow -compile

After running auto-generated tcl script, if there's no error then probably there's some problems with your tcl script so can do the comparison. If there's error with auto-generated tcl script as well, then probably the problem is in the design files.


Thanks,

Best regards,

Sheng

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer.


jeffshh056's avatar
jeffshh056
Icon for New Contributor rankNew Contributor
2 years ago

Hi Sheng,

My teammate who is using Quartus in GUI mode and got the same issue.

I am using quartus_sh, and I have package require ::quartus::flow in my TCL file. The flow actually runs but errors out.

Info: Run task: IP Generation (pass)

Info: Run task: Design Analysis(pass)

Info: Run task: Logic Generation(pass)

Info: Run task: Analysis & Synthesis(51 errors)

Error (16045): Instance "u_axi_bridge" instantiates undefined entity "axi_bridge" File: #######/src/xyz_ctl.sv Line: 2328
Error (16185): Can't elaborate user hierarchy "u_axi_bridge" File: ######/src/xyz_ctl.sv Line: 2328

What puzzles me is that

  • I do see the design "axi_bridge" gets compiled, I don't see compile error related to that module, why it can't elaborate?

I am attaching the syn.elab log file here, can you help take a look?

Thanks,

-Shu