New Contributor
Super ContributorHi,
You can export as HDL parameter. Then pass the generic with the command set_parameter check this link https://www.intel.com/content/www/us/en/docs/programmable/683432/22-4/tcl_pkg_project_ui_ver_1-0_cmd_set_parameter.html or using GUI by go to Assignments -> Settings -> Default Parameters
Thanks,
Best Regards,
Sheng
New ContributorHi,
Sry for late response. I tried it out. However, I don't see how I can pass this parameter from .qsf file to the IP module or take the value from the IP module. Maybe, I'm missing the connection here somewhat.
Kinda regards
Luigi
Super ContributorHi Luigi,
Just notice that this SPI Intel FPGA IP originally don't have any HDL Parameter so you can't pass this parameter from .qsf file to the IP module or take the value from the IP module.
Possible way is to manually create parameter for the slowcount in spi_spi_0_altera_avalon_spi_1923_przinoa.v check screenshot below and link that parameter all the way to top level wrapper. 128000 Hz having 196 clock pulses while 100000 Hz having 250 clock pulses. However, you probably can only pass this parameter to IP module but can't take value from IP module because that module will be getting changed back to original version when IP being regenerated. So may be you can export system as .tcl and read IP value from .tcl.
New ContributorGood morning Sheng
I see unfortunately that's what I wanted.
Kinda regards
Luigi
Super ContributorSeems like export the system in .tcl and compare, modify the values in .tcl will be more easier. Then use qsys-script command to source it. Then, run qsys-generate or Generate HDL in GUI.
