Partition that will be filled in by QDB file - shouldn't need an 'entity'

Note that I have also taken the Design Block Reuse training. The examples of 'black box' VHDL files in this training include the 'entity' declaration as well as 'architecture logic'. I am still confused as to why the black box must be defined in this way as opposed to the more common component declaration. I hope there is a way around this.

Even when I use the 'black box' VHDL from that training:

library ieee;
use ieee.std_logic_1164.all ;
entity sub is
port (
      input: in bit;
      clk : in std_logic ;
      output :out bit
	  );
end sub;
architecture logic of sub is
begin
end logic;

I still see the following error:

Error(19326): The partition "sub" is loaded from a Partition Database File (.qdb) and is set to preserve with a Preservation Level assignment. These two preservation types cannot be combined.

I first ran Analysis & Elaboration on 'simple'. Since I added in the entity and logic architectures, this succeeded and provided me with the hierarchy view that included the 'sub' instance. Finally, I set the 'sub' instance as a partition with Preservation Level=synthesized, pointed the QDB file to the one that was exported from the 'sub' partition in the 'sub' project (after adding a dummy top module to the 'sub' project - again I hope this is not the solution...). When I run Analysis & Synthesis, it gives the error mentioned above.

Again, any help is much appreciated.

-dbanks12