Partial Reconfiguration - JTAG Debug Mode

I found the solution since it was a pretty simple problem. The nreset was always connected to '0' by default leaving the state machine always in an IDLE state.

For those who'd like to make a simple test here is the VHDL instantiation that works properly in the JTAG mode.

PR_MEGAFUNCTION : PR_ip port map(

clk => clk,

nreset => '1', -- fix at '1'

pr_start => '0',

double_pr => '0',

freeze => freeze,

status => leds,

data => (others => '0'),

data_valid => '0',

data_ready => ready

);

However, it would be nice if more experienced partial reconfiguration designers give us some useful hints in this thread.

cheers,

Stef