parameter passing for IP in Platform Designer (Qsys)

The device is Stratix V and the bar space interface is memory mapped. I don't think these matter. I contacted local FAE about the issue. They are checking on whether it is possible to pass parameters into an instantiated QSys system. Our prior workaround has been to post-process the synthesized verilog file that is created after QSys generation step. The post-processing adds code for the parameters. FAE is checking to see if there is a more elegant way than post-processing with script.