--- Quote Start ---
Not to add another complication, but VHDL is, in my opinion, a horrible simulation language. When it comes to synthesis, VHDL and Verilog are a toss up as to which is the least stupid. For simulation, SystemVerilog is probably far superior to VHDL. Just printing out values is difficult in VHDL. Probably best to stick to VHDL simulation for VHDL code for now though. Tricky is far more knowledgeable in such areas and may have a different opinion.
--- Quote End ---
VHDL can do a hell of a lot, and life is made easier with VHDL 2008 (all standard types have to_string, to_ostring and to_hstring functions, for example). Most stuff you can do with SV you can do with VHDL. Where VHDL falls down compared to SV is re-use
I will admit that it can be a chore for some things in VHDL - if you write stuff away in packages it makes life easier and re-usable.
I am now someone who now writes testbenches in SV because of the re-use and stuff you get for free - but SV can get very confusing very quickly for a VHDL only engineer.
10 years writing testbenches in VHDL now has me libraries for reading/writing bitmap files at either 8 or 10 bit per pixel, plenty of stimulus generation, and I even built a generic linked list (ie. it will work with any type).
I highly recommend learning testbenches in VHDL. It was my knowledge of testbenching that helped me learn SV. It is not an easy thing to pick up if you are not already skilled in writing tests.
Honored Contributor
