Parallel VHDL

1. When I say farily standard, its just code similar to that Ive seen over the years. Beginners probably wont understand it - but any VHDL engineer with a year or twos experience should be able to work it out.

2. You can verify the results in the testbench. At a basic level you've probably got a set of stimulus, a set of expected results and you can just check them in the testbench. Then you could move on to writing a model of the ALU that runs in the testbench alongside the DUT, and then provide random stimulus so make the testbench self checking. As you move up in skill with testbenches you can model all kinds of things to packets to bus transactions etc, and sequence them all to cover as many situations as practical.