Honored Contributor
Honored ContributorHi Alexander,
The first thing to verify is that all of the IO related to the flash device are configured correctly and properly connected to the PFL implementation in your design. Even if there are errors here it will likely synthesize correctly, however, the communication with the flash device won't work. That was my experience and as soon as it was corrected everything worked fine. Mine was implemented as a schematic block, but, Cameron had issues with the generated code so use your PFL design is a schematic block rather than VHDL or Verilog instantiation, if it's not already. I hope this helps and you can find a solution to your problem.
