Forum Discussion
Altera_Forum
Honored Contributor
13 years agoNo solution for the exact error. However, I did confirm with the factory that in using the PFL IP utility and generating VHDL, it would not work correctly. I used the PFL IP utility and generated a schematic block and got it working. Seems to be a bug in code generation. I moved on. Sorry I am no help. Maybe someday someone will find an answer to this. I have seen that many have had the same problem.