Parallel adder timing issues

Hi Sam:

I agree with Rsync that TimeQuest is the way to go. It uses an SDC file that is very similar to the ASIC flow, and give you much more detail on the failing paths.

If the only thing you are synthesizing is a single adder directly connected to the IO's of the FPGA, I can easily see where you could be failing 266 MHz.

The IO cells are significantly slower than the core cells. Also you may loose lots of time if the input at output pins are located right next to each other in the design. (IE you may loose all your time, because the signals have to be buffered and routed all across the die.)

If you have your clock defined in the classic TAN, if you manually open up TimeQuest, it should auto-generate a very basic SDC file and run. Then you can get a better idea of the timing issues.

If you can simulate the RTL -vs- Gate and send a snapshot of what you're seeing for latency, maybe that could shine some light as well.

One other problem, might be the SDF file isn't getting imported properly into the gate level simulation. Then all the cells will default to a very pessimistic delay, causing you all kinds of problems.. (I though it use to be 100 ns.. But if it's 10 ns, that would cause your 3 cycle delay).

Since you're doing gate level simulation, you could also see where the delay is coming from by looking at the input's output, and the input and output of the registers.

That way you could measure the delays and compare vs TimeQuest

Pete