Parallel adder timing issues

If you're an ASIC guy and have any Primetime/Design Compiler experience, I would use TimeQuest instead. Enable this by going to Assignments -> Settings -> Timing Analysis Settings and enable TimeQuest. It is similar to Primetime and uses SDC(Synopsys Design Constraints) as the input constraint file. There will be a learning curve with it, but I strongly recommend going through the documentation. In fact, since your new to Classic Tan, I would recommend completely ignoring it and using TimeQuest, since that is the timing analyzer that will support newer families. (It's really head and shoulders above Classic TAN for what it can do, but it takes a few constraints to get it going.)

As for the 3 clock cycles, I haven't looked at it and maybe anakha will chime in. You might want to examine internal registers to see exactly where the data is on each clock cycle.

On that note, most users don't do timing simulations. They do RTL sims(which shows latency and functionality), and then do static timing analysis. If RTL shows 2 clock cycles, and you meet static timing analysis, then your timing sim would just show the same thing, 2 clock cycles. (IO timing is part of static timing analysis, and again needs to be done with a full round-trip analysis, which is what TimeQuest is designed to do.)