Parallel adder timing issues

Thanks. I am understanding the reasons not to meet timing now slowly.

My question is, Why in simualtions output is showing after 3 clock cycles, when TCO is around 1.85 clock cycles.TSu.Th is around 1 clock cycle or less than clock period. I used the above anakha rtl code to synthesis.

Second request is , is there any other timing constraints need to set apart from Clock (266mhz) to meet timing?. Sorry ..I was ASIC guy working in FPGA first time. I know timing constraints setup very well, but doesnt know in FPGA terms. It will be great help if any one help to solve this issue. Same adder is working in my ASIC libs with 90nm technology around 1Ghz and unable to synthesize for 150mhz in FPGA. There is some mistake in FPGA constraints.

--Sam