Parallel adder timing issues

Thanks for your answers. I tried the RTL adder also instead of mega function. Even then at 266mhz frequency, in simualtion output is after 3 clock cycles.

Can any one explain, how to find out the module working frequency in altera FPGA reports. My assumption is critical path will give us the rough estimation of clock frequency. Can any one explain how to find critical path for design.

I am using classic timing analyzer and specifying only clock freq is around 266 mhz. Is there any constraints will help to meet timing and better optimization?. Currently Tco is showing around 6.5 ns, which is 153mhz.

--Sam