Parallel adder timing issues

Hi Sam:

I don't know your entire system, but by your description, I would look in the following areas:

1) Doing the add at 266 MHz should be fine as long as both input and outputs are registered. Although you can do this adder using the megafunction wizard, This is a very basic function, that I would suggest you do in strait verilog or vhdl. For verilog this would look like the following:

module adder10bit (

input clk_i,

input reset_i,

input signed [9:0] A_i,

input signed [9:0] B_i,

output signed [10:0] Sum_o

);

reg signed [9:0] A_r;

reg signed [9:0] B_r;

reg signed [10:0] Sum_r;

wire signed [10:0] Sum_c;

assign Sum_o = Sum_r;

assign Sum_c = A_r + B_r; // Actual adder

always @(posedge clk_i)

begin

if (reset_i)

begin

A_r = 10'd0;

B_r = 10'd0;

Sum_r = 11'd0;

end

else

begin

A_r = A_i;

B_r = B_i;

Sum_r = Sum_c;

end

end

endmodule

Once you synthesize this block with the correct timing constraints, it should be able to do the 266MHz with no problem on Stratix II.

It will have a clock Latency of 2 clocks, but can have a new result every clock cycle.

My guess is, that your primary delay is in the input or output paths: IE IO buffers have lots of delay, so by the time you reach the adder, you've already used up most of you clock cycle. If 1 cycle latency is necessary, you can try replacing the above module with this one:

module adder10bit (

input clk_i,

input reset_i,

input signed [9:0] A_i,

input signed [9:0] B_i,

output signed [10:0] Sum_o

);

reg signed [10:0] Sum_r;

wire signed [10:0] Sum_c;

assign Sum_o = Sum_r;

assign Sum_c = A_i + B_i; // Actual adder

always @(posedge clk_i)

begin

if (reset_i)

begin

Sum_r = 11'd0;

end

else

begin

Sum_r = Sum_c;

end

end

endmodule

This will have the 1 cycle latency you want, but not the cycle time is limited by the input data path. If you have a lot of combinational logic here, you could be stuck.

Always make sure your clocks are defined in your SDC file. If the clock is not defined properly, you could be failing because synthesis is just not optimizing the path for that high of speed.

Hope this helps.

Pete