packages for synthesis

Using Quartus 15.1

I am trying to define my own types for IO in my modules.

I have generated the package foo_pkg.sv as follows:

package FOO_BUSSES;

typedef struct packed{

logic rd_wrn;

logic [31:0] address;

logic [10:0] burstsize;

logic transaction_dv;

logic dout_dv;

logic [63:0] dout;

logic din_dv;

logic [63:0] din;

logic transaction_rd;

logic din_rd;

} foo64_intf_p ;

endpackage // FOO_BUSSES

Now that I have the package defined I want to call it into the module foo_top.sv

module foo_top

import FOO_BUSSES::*;

# (parameter A = 1,

parameter B = 2)

( input CLK,

input RST,

foo64_intf_p FOODEF

);

....

endmodule

When I synthesize I get the following error

Error (10161): Verilog HDL error at foo_top.sv(nn): object "foo64_intf_p" is not declared

in my qip that calls these mods:

set_global_assignment -library "foo_flex" -name SYSTEMVERILOG_FILE [file join "../../ip_foo/foo_common/rtl/foo_pkg.sv"]

set_global_assignment -library "foo_flex" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "foo_top.sv"]

this code will simulate using various modelsim simulators.

any and all help will be appreciated.