output Signal is not constant

You have SCL and NSL as inout ports, but it looks like you never use them as input pins. Do you intend process pros1 to get these signals from process trans and intend never to use these pins as inputs? If you are also driving these pins on the board but synthesis permanently enabled the tristate buffers, then that will cause problems. Check for synthesis messages like these:

--- Quote Start ---

Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus SCL~30 that it feeds

Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus NSL~30 that it feeds

Info: One or more bidirs are fed by always enabled tri-state buffers

Info: Fan-out of permanently enabled tri-state buffer feeding bidir "SCL" is moved to its source

Info: Fan-out of permanently enabled tri-state buffer feeding bidir "NSL" is moved to its source

Warning: TRI or OPNDRN buffers permanently enabled

Warning: Node "SCL~644"

Warning: Node "NSL~588"

--- Quote End ---

With SCL in process pros1 being driven by a register in process trans, SCL is a ripple clock. Check your timing analyzer messages for that. You probably have clock hold violations for paths from the NSL register in the clk domain to the counter registers in the SCL ripple-clock domain being synchronously cleared by NSL. See my posts at http://www.alteraforum.com/forum/showthread.php?t=754 for more information about ripple clocks.

In more than place you use this coding style:

if my_signal = '1' then
  <do something>
end if;
if my_signal = '0' then
  <do something else>
end if;

I would use this style instead:

if my_signal = '1' then
  <do something>
else
  <do something else>
end if;