Forum Discussion
CJT
New Contributor
New Contributoroutput or inout port "outA" must be connected to a structural net expression
//block1
module block1 (clk, inA, outA, outB, outC);
input clk, inA;
output outA, outB, outC;
reg outA, outB, outC;
always @ (posedge clk) begin
outA = inA;
outB = outA;
outC = outB;
end
endmod...
IntelSupport
Contributor
ContributorHi Chee,
May I know if there is any update from previous reply
p/s: If any answer from the community or Intel Support are helpful, please feel free mark and solution, give kudos and rate 5/5 survey.
