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Altera_Forum's avatar
Altera_Forum
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8 years ago

output doesn't toggle when simulating with other entities in Modelsim

Hi, I'm working on a vhdl testbench to simulate the behaviour of an I2C bus. I started with an original code (written in verilog) that works, made some changes to it an simulate it's behaviour as a s...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Here it is, I commented the two portions of the code where I'm seeing the issue: 


        state <= 8'h07;                    // signal    
        sda_o_e <= 1'b0;                 // other_signal

and 


                sda_o_e <= 1'b1;         // signal
                state <= 8'h81;              // other_signal

assign at the bottom: 


assign hps_sda_o_e = state;            // change from assign hps_sda_o_e = sda_o_e;