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Altera_Forum's avatar
Altera_Forum
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8 years ago

output doesn't toggle when simulating with other entities in Modelsim

Hi, I'm working on a vhdl testbench to simulate the behaviour of an I2C bus. I started with an original code (written in verilog) that works, made some changes to it an simulate it's behaviour as a s...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Hi, here is the code that works fine by it self: 


if (condition_1) begin
  signal <= '1';
end 
if (condition_2) begin
  signal <= '0';
end
assign output <= signal;

The conditions are met both when simulating as a stand alone unit and embedded, the problem is, when embedded on a test bench, even though the conditions are met, the output doesn't toggle, this fix made it work: 


if (condition_1) begin
  signal <= '1';
  other_signal <= '1';
end 
if (condition_2) begin
  signal <= '0';
  other_signal <= '0';
end
assign output <= other_signal;