Out of global clocks - Routing of reset signals

Hi,

I'm having a problem with my design.

I'm getting failed compilation runs or very big neg. time slacks.

It seems that this is caused by Quartus running out of global clock nets.

Having looked into the Fitter report, it seems that half of the 20 global

clock nets are "blocked" by reset signals - being generated by the

SOPC system as "... domain_synch_module....data_out".

Is there a way, I can handle this problem, using multicycle-commands

for the reset signals or something like that?

If you think "Newbie, RTFM!!!", please give me a hand (and a link to it).

I'm more than willing to find out the right way to cope with multiple clocks

and a better reset handling.

Best regards,

Roman Dietrich