Organizing hdl sources through .qip file

Hi all,

Probably this is a very simple question but I couldn't figure out how to do it in Quartus.

I have a design with a sopc module, a few MegaWizard modules and other modules I've written in Verilog/VHDL.

I can see that hdl files used by Sopc and Megawizard modules are grouped in Quartus project file list under a qip file header, which acts as a folder in a file tree.

On the other hand my .v and .vhd files are listed without any hierarchical structure, then making very difficult to understand which module each file belongs to.

How can I group module files like sopc or megawizard?

Should I manually write a qip file or is there an automatic function available in Quartus?

Regards

Cris