Forum Discussion

tde_m's avatar
tde_m
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Ordering of channel operations

Hello, I'm currently struggling with enforcing the order of write/read to channels. I know, from the Intel programming guide, that two independent channels operation can be re-ordered by the compil...
Douglas_P_Intel's avatar
Douglas_P_Intel
Icon for New Contributor rankNew Contributor
6 years ago

Hi,

This is expected behavior. Within a kernel, multiple channel calls (to different channels) are considered independent. This can be a problem if channels form a cycle between kernels.

When I compile your code, the compiler generates a warning as follows: (check your log files)

  • Compiler Warning: Kernels comp and generator may form a cycle due to connectivity of channels channels[0] and channels[1]. Use mem_fence if you require source code-based ordering of channel operations. Channel depths cannot be optimized.

Ideally, you want to avoid forming a cycle between kernels with channels.

https://www.intel.com/content/www/us/en/programmable/documentation/mwh1391807965224.html#mwh1391806067772

HRZ's avatar
HRZ
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

@douglas.prinn​ The "receive" kernel has a clear Write-after-Read hazard/dependency on "status->m". The two operations involving the variable, regardless of what those operations are, should not be reordered (by any sane compiler). The existence of a cycle a channels in this case, or channel operations for that matter, is irrelevant. Are you implying that aoc ignores data dependencies when channel operations are involved?