OR condition acts like an AND in Verilog?

The code doesn't register save_data in a reliable way. The latch must be expected to react on glitches in the counter output. Don't jump into conclusions about Verilog from a bad synchronous hardware description.

I also notice that you don't show compilable code, CLOCK_50 is e.g. undefined. Thus the original code may have additional issues.

The save count block should at minimum use a synchronous @posedge CLOCK_50 condition. But there may be still a problem of synchronizing pulse_in to CLOCK_50, which goes beyond the scope of this thread, however.