Honored ContributorI'm doing some analysis with SignalTap and I'm wondering if I can set some sort of flag in the compiler to make it not synthesize away some signals that are currently not routed anywhere in the design but I would still like to view their values.
Honored Contributortake a look at the noprune synthesis attribute
Honored ContributorAnd where do I set that in Quartus II?
My design is all VHDL. Nevermind, found it. http://quartushelp.altera.com/current/mergedprojects/hdl/vhdl/vhdl_file_dir_noprune.htmHonored ContributorDon't forget to open your VHDL/Verilog in Quartus II and go to Edit -> Insert Template. I find this the best place to look at what's possible. I also put "keep" attributes on a combinatorial node that won't get synthesized out, but might get merged with other combinatorial logic and hence something I can't find in the post-fit netlist.
