Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Optimisation issues

Hi, is there any way to find out WHY Quartus is optimising away stuff? I know I've almost certainly got something wrong in my VHDL, but I've found that several of my signals/registers are 'missing' o...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

I forgot that you only get a warning when the synthesizer optimizes a signal away because it doesn't drive any signal. In the other cases, signals can be optimized away without warning. For example: 

  a<= b and c;
  b <= d and e;
In this case (provided b isn't used somewhere else) the simulator will generate the a signal using a single LUT and the c,d and e signals. b will be optimized away. If you want to read it from Signaltap you will need to put a "preserve" attribute on the signal to prevent if from going away (IIRC connecting it to Signaltap in pre-synthesis isn't enough).