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BTW - I think I've found why the FPGA isn't working, and it wasn't an optimisation issue, it was a timing one. It'll have to wait until I get home tonight before I can test it out, but the mistake I've found makes sense.
But I'm still not sure if I should have been able to do what I wanted in SignalTap - if I had been, I think I'd have found the problem sooner. I think my confusion with that lead me to wasting time investigating in the wrong places. I think I may need to experiment a bit more to see if I can work out how SignalTap is handling the signal naming.
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timing problems + signaltap is a very bad mixture since signaltap logic adds more logic and may mislead you if timing is not right.
Modelsim testbench is best to check functionality and add to it a successul STA closure and it should work first time in the chip...with a bit of prayer!
If you have to use signaltap make sure design passes timing. Use minimum space for testing and you can force nodes to stay using keep attribute or connect to unused pins or other measures specific to signaltap tool itself (which I am no expert).
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