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Altera_Forum
Honored Contributor
Honored ContributorOptimisation issues
Hi, is there any way to find out WHY Quartus is optimising away stuff? I know I've almost certainly got something wrong in my VHDL, but I've found that several of my signals/registers are 'missing' o...
Altera_ForumHonored Contributor
Honored Contributoryou then need to recompile it. It cpould be the "signaltap-presynthesis" option
