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Altera_Forum's avatar
Altera_Forum
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11 years ago

Optimisation issues

Hi, is there any way to find out WHY Quartus is optimising away stuff? I know I've almost certainly got something wrong in my VHDL, but I've found that several of my signals/registers are 'missing' o...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Yes, if I choose Design Entry (all signals) then they're there, but appear in red.

I'm wondering if (the name of) a signal which is just there to pass a data from one component to another will just be deleted because it's the same as the source component's output signal.