Altera_Forum
Honored Contributor
Honored Contributoropenmp with Quartus II
How would Quartus II software recognize openmp pragmas? suppose there is a C code with parallelization pragmas, how can this be ported on the FPGA?
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Altera_ForumHonored Contributor
Honored ContributorMost designs are based on VHDL or Verilog, and possibly schematic or AHDL languages, which are all inherintly parallel. There are some other companies who synthesize "C to gates", but the output of those tools are an HDL that Quartus synthesizes. The other option is to put a Nios II/SOPC system into your design(which is still HDL underneath the IP), but then run your C on the soft processor. You can then do hardware acceleration with custom instructions or the right-click accelerate options.
Are you doing a Nios design with OpenMP pragmas in it, or something else? (If so, you may want to post this to niosforum, as you'll probably get a better response...)
