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I'm not sure what you're trying to do in your first question, but as far as your second question is concerned, the answer is no. The BSP (the board_spec.xml file you mention) is responsible for configuring the I/O and creating "space" on the FPGA for the kernel hardware, which is created by compiling your kernel code with aoc. You can create OpenCL libraries that include RTL code, but there is no way to add or change the I/O of the device through OpenCL.
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Thank you very much for your answer. So the BSP (board_spec.xml) can be used to add more IO pins or interfaces, and then they will be available to use in openCL?
Concerning to first question. Ina general way I am asking for the correct work flow to develop a project by using OpenCL and IP or vhdl modules working together.
For instance, suppose that I want a project as the "hello world" example with the variation of modify the frequency of leds, to achieve this I compile the hello world example without do a complete compilation (not building hardware) and as result the aoc compilator generate me a .aoco file with the name of project and a folder with quartus project inside, now I can modify the frequency of leds by editing the verilog code from the quartus project generated, and then I save this and perform a complete compilation "building hardware" using .aoco file and quartus project modified in the folder. At the end I achieve the building of the project but I am not sure if this is the correct way because I can achieve the same task by editing in the altera board package folder the quartus project template and edit in the same way. I am pretty confuse with the correct work flow to develop a opencl project with cyclone v fpga.
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