OpenCL for Arria 10 in Quartus 15.1

SV is easier to port from 15.0 and 15.1. You will still need to update the IP to the newer version of Quartus, but that is typical in FPGA design. THis is also something that you only need Quartus Prime standard for. As for how much faster...depends on the code and how many floats you define. On average a 4x improvement from SV to A10 is common, but with alot of floats defined, I have seen an 8-10x improvement (specifically on things like genomics and CNN algos)

QHD = Quartus Heirarchal Design. A new feature in Quartus Pro Prime that allows building FPGAs hierarchally with timing closed, logic locked, and hardware preserved partitions that are IPXACT compatible

PR = Partial reconfiguration. A method of reprogramming the FPGA dynamically...the most common case is over PCIe