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FCive's avatar
FCive
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

OpenCL error on code compilation

Dear all, I would like to use OpenCL SDK for a Terasic DE5-Net to deploy my algorithm (I am using Quartus 18.1 and OpenCL SDK 18.1). I successfully run the examples provided by Intel FPGA for OpenCL...
FCive's avatar
FCive
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

Thank you HRZ.

I tried to reduce the number of the loops and also the number of variables. Finally, I was able to compile without the previous error. Unfortunately my design is still too big to fit into the FPGA. In particular, there are some variables that requires too much logic utilization. For example, I have the variable 'xtmp1', which is an array of 16 elements of 16 bits each, and in the report I can see the following comment:

Private Variable: - 'xtmp1' (fft1dint.cl:393):

  • Type: Register
    • 512 registers of width 16 and depth 1
    • 256 registers of width 16 and depth 7 (depth was increased by a factor of 7 due to a loop initiation interval of 7.)

Why the compiler uses such a big number of registers for 'xtmp1' variable? How can I reduce the resources for this variable?

Federico