OpenCL + Cyclone V SoC

It seems the new Cyclone V GSRD doesn't work on the SoCKit straight out of the box. It tells me:

dwmmc_socfpga ff704000.dwmmc0: regmap for altr,sys-mgr lookup failed.
platform ff704000.dwmmc0: Driver dwmmc_socfpga requests probe deferral

The SoCKit specific version is currently password protected on RocketBoards: http://www.rocketboards.org/foswiki/documentation/gsrdusermanualarrowsockitedition

Does that mean it's still being worked on? I've now received an evaluation licence for Quartus II, and OpenCL no longer complains about that. I think I have everything configured right, but it now tells me:

$ aoc hello_world.cl --board c5soc
Warning: Unused kernel argument 'acl.printf.buffer.start'
Warning: Unused kernel argument 'acl.printf.buffer.size'
Internal Error: Sub-system: DEV, File: /quartus/ddb/dev//dev_basic_info.cpp, Line: 617
Error: Qsys-script FAILED.
Refer to hello_world.log for details.

and the log file says:

2013.11.26.09:23:47 Info: Doing: <b>qsys-script --script=system.tcl --Xmx512M --XX:+UseSerialGC --system-file=system.qsys</b>
Internal Error: Sub-system: DEV, File: /quartus/ddb/dev//dev_basic_info.cpp, Line: 617
BASIC_INFO's HDR file /opt/altera/13.1/quartus/common/devinfo/stratixv/ddb_stratixv_gxf5_es_hdr.ddb not installed

It's right about me not having any Stratix V stuff installed yet, but why should it need it when I'm attempting to build for the Cyclone V?

I'm making progress of a sort. I persuaded 3.9 to run on a SoCKit as follows:

1. Start with the new 3.9 SD card image for the Altera Cyclone V dev board from: http://www.rocketboards.org/foswiki/documentation/gsrdreleasenotes

2. Replace the preloader, DTB and RBF with versions copied from the SoCKit Linaro build found at: http://www.rocketboards.org/foswiki/projects/sockitlinarolinuxdesktop

3. Clone git.rocketboards.org/linux-socfpga.git, check out socfpga-3.9.rel, then built a fresh zImage which is also copied onto the SD card

That allowed me to boot 3.9 on my SoCKit, and installing the Quartus Stratix V drivers allowed me to finally build the OpenCL "Hello World" example. Unfortunately when I run it Linux unceremoniously crashes!

root@socfpga:~# ls
README            aclsoc_load       altera            hello_world.aocx
aclsoc_drv.ko     aclsoc_unload     hello_world       user
root@socfpga:~# ./aclsoc_load
root@socfpga:~# ./hello_world
Reprogramming was successful!
FPGA is in user mode. Enabling bridges

or alternatively:

root@socfpga:~# ./aclsoc_load
root@socfpga:~# ls /dev/a*
/dev/acl
root@socfpga:~# ./user
Opened the device: file handle# 3!
Unhandled fault: imprecise external abort (0x406) at 0x76ec786e
Internal error: : 406  SMP ARM
Modules linked in: aclsoc_drv(O)
CPU: 1    Tainted: G           O  (3.9.0-00161-ged01b8c# 4)
PC is at aclsoc_read_small+0x44/0xf4 
LR is at aclsoc_rw+0x38c/0x3ec 
pc :     lr :     psr: 60000013
sp : bf1efeb0  ip : 00000000  fp : bf1efec4
r10: 00000018  r9 : bf1ee000  r8 : 00000000
r7 : bf1efef8  r6 : 00000002  r5 : bf0cb600  r4 : 00000001
r3 : 00000000  r2 : 00000001  r1 : 7edbfc5f  r0 : c09d0000
Flags: nZCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment user
Control: 10c5387d  Table: 3fb2c04a  DAC: 00000015
Process user (pid: 698, stack limit = 0xbf1ee240)
Stack: (0xbf1efeb0 to 0xbf1f0000)
fea0:                                     00000000 00000018 bf1eff3c bf1efec8
fec0: 7f001d08 7f001660 bf1efef4 00000001 00000004 00000007 bf1ee000 bf0cb64c
fee0: 76e5a7bc bf1effb0 c09d0000 00000001 bf1effac 00000000 00000000 00000000
ff00: 00010000 7edbfc5f 00000001 00000000 802a65ac bf13b000 7edbfc44 bf1eff78
ff20: 7edbfc44 00000000 bf1ee000 00000018 bf1eff54 bf1eff40 7f001d8c 7f001988
ff40: 00000001 00000018 bf1eff74 bf1eff58 800f143c 7f001d74 bf1eff78 00000000
ff60: 00000000 bf13b000 bf1effa4 bf1eff78 800f1554 800f13a4 00000000 00000000
ff80: 00000000 7edbfd08 0000849d 00000003 8000ea08 00000000 00000000 bf1effa8
ffa0: 8000e7c0 800f1514 00000000 7edbfd08 00000003 7edbfc44 00000018 7edbfc44
ffc0: 00000000 7edbfd08 0000849d 00000003 00000000 00000000 76f06000 00000000
ffe0: 00000000 7edbfc2c 000085c9 76e8a1cc 40000010 00000003 3200004a 0002f7d2
 (aclsoc_read_small+0x44/0xf4 ) from  (acls)
 (aclsoc_rw+0x38c/0x3ec ) from  (aclsoc_rea)
 (aclsoc_read+0x24/0x2c ) from  (vfs_read+0)
 (vfs_read+0xa4/0xe4) from  (sys_read+0x4c/0x80)
 (sys_read+0x4c/0x80) from  (ret_fast_syscall+0x0/0x30)
Code: e24bd00c e89da800 e5d0c000 f57ff04f (e1a0000d) 
------
aclsoc_close (191): 
aclsoc = bf0cb600, pid = 698, dma_idle = 1

Hello Jim,

Please contact your local sales or FAE representative. The reason why the SoC support is not documented on the web is because there is a patch that needs to be applied which comes with the documentation.

So, many of the questions you are asking are valid, but I want to make some clarifications.

Yes, C2H is gone and OpenCL is NOT C to gates. You are right it is a higher level coding language than HDL, but its intention is not to produce HDL code that can be incorporated into an FPGA (that is something that is coming as a new front end to our current flow). It is intended to allow a programmer the ability to take an algorithm in C or CUDA and easily implement it in an FPGA to achieve system level acceleration of that algorithm. It abstracts away the low level HDL coding language and tool flow and allows parallelism to be extracted from OpenCL C code.

SoC is available in 13.1 of Altera's tools. It is a customer beta feature that requires a patch to fix a couple of things in the compiler for Linux, but allows a programmer to profile their inner loops and functions they want to accelerate and push those onto the FPGA fabric without having to learn HDL. IN this case, it is real time acceleration vs system acceleration. Altera abstracts away not only the HDL flow, but also the ARM flow too. The Altera SDK for OpenCL produces both the ARM host and the FPGA accelerator image in one step. I am about to release a new webex that goes over the SoC implementation on the Altera OpenCL page.

If you want the code to the Raytracing demo, it is available upon request. You just have to contact your local Altera FAE and he can request it from me, and I will distribute it. It is nothing fancy, just showing single chip host and FPGA accelerator solution. It is a demo more than a design example. There is a design example page on the Altera.com OpenCL page that has a lot more interesting things to play with. There is also a facial detection design example that will be released this week or next, that we used at SC13 a few weeks ago and is kinda cool (but wont run on SoC)

Altera SDK for OpenCL requires a license that also has to be requested through an Altera sales or FAE rep. You can get a 60 day eval license to play with it, but will need a board to compile for and run on. Also on the Altera.com OpenCL page is a link to our supported board vendors that have COTS boards that can be purchased and used. The Arrow SoCKit board support package is still undergoing the approval processes to be a OpenCL supported board, but the raytracing demo has already been ported to it by Arrow. Be aware that the Cyclone V SoC is not a large part and real time acceleration of simple functions will be possible compared to a non SoC part which is scalable.

Hi,

Is there any documentation avalible for openCL on SOC soon?, do I need to make my own preloader, uboot and dtb from the generated qsys-files from the aoc? It would be nice with a working SD image example for both alteras cyclone V soc development kit and arrows sockit.

Being a beta feature means documentation is available upon request. You build the host code just like you would for any other host. FOr SoC, that requires a little more effort, as you mentioned...preloader, uboot..etc. THe key functions to be accelerated in OpenCL using the Altera SDK.Arrows SoCKIT board is going through testing now and will be released shortly as a preferred board. They have ported a raytracing algorithm already...and the basic design examples on Altera web page (matrix multiply, vector add...etc) also run on their card. This is all to be released in the next several weeks or for the 14.0 release more officially.Alterass design examples page is the way to get code to run...It is up to the Altera preferred baord vendors to port the code and get it working on thir boads, so contacting them is the way to get that image for their board.

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Hi, Is there any documentation avalible for openCL on SOC soon?, do I need to make my own preloader, uboot and dtb from the generated qsys-files from the aoc? It would be nice with a working SD image example for both alteras cyclone V soc development kit and arrows sockit.

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Arrows SoCKIT board is going through testing now and will be released shortly as a preferred board. ... This is all to be released in the next several weeks or for the 14.0 release more officially.

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Hi,

the quartus 14.0 is out and mentinons the SoC board, but not the affordable SoCKit. And I've just noticed there is a new DE1-SoC board. Are there any details about support for these boards?

Thanks.

--- Quote Start ---

Hi,

the quartus 14.0 is out and mentinons the SoC board, but not the affordable SoCKit. And I've just noticed there is a new DE1-SoC board. Are there any details about support for these boards?

Thanks.

--- Quote End ---

The Altera OpenCL Compiler is board agnostic. You can compile kernels for the CV SoC device, but to use OpenCL on the board, you need a BSP for that board. Altera has released reference platforms to get people started building the IO ring for their custom boards and Altera's partners have been porting the reference platforms to their own boards. So, currently the Altera CV SoC Dev kit is the only CV SoC board that has a BSP...Arrows is in progress and as far as I know, the DE1 board doesn't, but you would just contact them and ask them for the BSP to download for it.

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Thanks for your suggestions eyguacel,

After a rather frustrating Saturday afternoon I now have yet another flavour of embedded ARM Linux on my hard drive! The RocketBoards Linaro SD image seems to function OK on my SoCKit, but their git server also seems to be non-functional at the moment. I've been using the toolchain that came with the Altera version of ARM DS-5 from /opt/altera/13.1/embedded/DS-5/bin, although I had to build my own mkimage. I eventually found what looks to be a clone of the RocketBoards repo, and did this:

git clone git://support.criticallink.com/home/git/linux-socfpga.git
cd linux-socfpga
git checkout socfpga-3.8
make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- socfpga_defconfig
make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- LOADADDR=0x8000 uImage

I replaced the uImage on the SD card with my new one (which did of course kill my nice LXDE desktop), and built the driver and hello_world following your instructions. Where is pkg_editor.h hiding do you suppose?

Transferring that lot to the SD card as well revealed this:

root@localhost:~# ./aclsoc_load
./aclsoc_load: 21: [: 251: unexpected operator
root@localhost:~# ls /dev/acl
/dev/acl
root@localhost:~# ./hello_world
Reprogramming was successful!
FPGA is in user mode. Enabling bridges
sh: 1: cannot create /sys/class/fpga-bridge/fpga2hps/enable: Directory nonexistent
sh: 1: cannot create /sys/class/fpga-bridge/hps2fpga/enable: Directory nonexistent
sh: 1: cannot create /sys/class/fpga-bridge/lwhps2fpga/enable: Directory nonexistent
PCIe-MMD Fatal: Version mismatch, expected a0c7c1e0 but read 0
hello_world: acl_pcie_device.cpp:217: ACL_PCIE_DEVICE::ACL_PCIE_DEVICE(ACL_PCIE_BOARD*, int): Assertion `.
Aborted
root@localhost:~#

Does anyone from Altera pop in here on a regular basis to assist? I don't know if this is good form or not, but I've sent them a "Service Request". I have yet to receive a reply however.

As I mentioned at the top of the thread, I'm new to all things Altera. I've seen the SoC publicity, and gained the impression that it's possible to evaluate all their development tools free of charge on "entry level" hardware. Maybe that doesn't apply to OpenCL, or maybe it's an inadvertent "feature" that's easily fixed?

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Hi Jim,

I encountered the same problem.

pcie-mmd fatal: version mismatch, expected a0c7c1e0 but read 0

hello_world: acl_pcie_device.cpp:217: acl_pcie_device::acl_pcie_device(acl_pcie_board*, int): assertion `.

aborted

How did you solve that? Thanks.

Hello, fellows.

Has anyone made some progress in this matter? I'm starting to work with an Arrow SocKit and I'm very interested in working with OpenCL in it, but I didn't found any consistent documentation for this. I'd like to know if any of you has made some progress and if you kindly could point me where to begin. I'm familiar with CUDA and have little knowledge of OpneCL as well.

Thks!