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Altera_Forum
Honored Contributor
12 years agoOpenCL + Cyclone V SoC
Hello, Whilst I have lots of experience with embedded ARM C/Linux I'm new to FPGAs and new to OpenCL. I have a SoCKit plus some no doubt dumb questions: 1. It seems C2H is no longer suppor...
Altera_Forum
Honored Contributor
12 years agoHello Jim and everybody
I'm facing the same problem :-( I have seen Altera has included "beta support" for cvsoc but it is not documented at all. I have compiled host side driver for cvsoc (no pkg_editor.h header so reprogram app is commented out in Makefile). I put the module (aclsoc_drv) in my altera_cvsoc kit and "insmoded" it. Everything seems to be ok until the driver tries to register an IRQ This is my dmseg output aclsoc_init (826): ----------------------------<7> aclsoc_init (827): Driver version: 13.1.1<7> aclsoc_probe (705): acl_board_id is 4, ACL_PCI_CRA_BAR is 0, PAGE_SIZE is 4096<7> init_chrdev (130): aclsoc = 251:0<7> mapped region 0 (lw) to [c0a80000, c0aa0000). Size = 131072 mapped region 2 (lw) to [c0a00000, c0a40000). Size = 262144 mapped ffc25000 to c0a60000 Writing 0x3fff to offset 0x80 Writing 0x0 to offset 0x7c Setting applycfg bit to 1 ALT_SDR_CTL_CTLCFG_OFST = 0xa8c42 ALT_SDR_CTL_CTLWIDTH = 0x2 ALT_SDR_CTL_PORTCFG = 0x0 ALT_SDR_CTL_FPGAPORTRST = 0x3fff ALT_SDR_CTL_REMAPPRIORITY = 0x0 ALT_SDR_CTL_CPORTWIDTH = 0x44000 ALT_SDR_CTL_CPORTWMAP = 0x2c000000 ALT_SDR_CTL_CPORTRMAP = 0xb00000 ALT_SDR_CTL_WFIFOCMAP = 0x980000 ALT_SDR_CTL_RFIFOCMAP = 0x760000 fpga_mgr mapped to c08e8000, fpga_mgr_data mapped to c08ea000 init_irq (288): aclsoc = bf043c00<7> init_irq (289): get_interrupt_enable_addr = c0a04050<7> init_irq (305): Could not request IRQ# 72, error -22<7> After failing to register the IRQ, the module remains in memory but the /dev/acl entry is not created. No test to try :-) Is Altera going to document cvsoc CL support in 13.1 or we have to wait for other version/service pack? Thanks In Advance