One segment vs two segment State Machine style

It seems to me that the thread is departing from the initially gained insight that functionally equivalent logic will result in almost identical resource usage. It are the functional differences that matter, e.g. registering or not registering output signals. It has been sufficiently clarified that user requirements are different in this regard. Properties that are considered as advantage by one are unwanted by others. In so far I'm not sure if additional analyses of single versus dual process state machines will bring essentially new results.

State encoding is a special point. For most FPGA FSM designs, the default one hot encoding is just fine. Besides timing, it's also the decoding effort for binary and similar compact encodings that must be counted. My personal favourite for all critical state machines is "safe" encoding, which uses also one state hot representation.

Splitting FSM in partial machines may be reasonable in some cases, but "form follows function". I won't do it to save a few LEs.

I started programmable logic design more than 30 years ago with small GALs and know that tiny CPLD design has other constraints. A CPLD FSM don't use the one state hot default, and it might be necessary to taylor a design down to the function of each register. Thus I won't refer the discussion primarly to CPLD design.