Honored Contributor
Honored ContributorThe two-process FSM has the advantage of being able to generate 'combinatorial' outputs which are often necessary, e.g. for the 'valid' and 'ready' signals in ST-modules. In the case of a single-process FSM you still have to maintain a second (combinatorial) process to generate this kind of outputs. As you now have to 'copy' some of the transition rules over from the synchronous FSM, you end up with two separate processes which can generate a harder debugging chore than weeding out the latches (which Quartus II warns you about).
I personally use two-process FSMs 9 times out of 10. I almost never use embedded counters in the FSM but instantiate external components, this produces nicer RTL diagrams. I once spent a lazy Sunday afternoon writing up a contrived example to test this. See the attached .qar.zip. The results are (for Cyclone IV E, auto device): style les registers mhz Two-Process 44 17 386 Synchronous 46 17 378 Hybrid 36 16 380 Hybrid JosyB 35 16 380 Note that the example doesn't have combinatorial outputs.
