One segment vs two segment State Machine style

Functional equivalent designs can be expected to give identical or at least almost equal gate level implementation.

The shown examples are functionally different in two regards:

- outp is registered in the single process style FSM and combinational in the "two segment" FSM

- count works different, resulting in 3 versus 4 counter bits

The resource count is different by only one 1 LE in Cyclone 3/4

Choosing one or the other style for resource usage efficiency makes no sense.

Personally I prefer single process style for this reasons

- visual representation of FSM behaviour, particularly with additional registered signals, may be internal signals like counters or design outputs

- no risk of unintentional latch generation by lack of attention

- FSM outputs are automatically registered as usually wanted