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Hello!
I'm trying to use the matching-case syntax introduced in vhdl 2008 but I'm having a bit of a problem. Take the following piece of code, say a register map for example:
clk : in std_logic;
rst : in std_logic;
addr : in std_logic_vector(7 downto 0);
reg0 : out std_logic;
reg1 : out std_logic;
reg2 : out std_logic;
reg3 : out std_logic
....
process (rst, clk)
begin
if (rst = '1') then
reg0 <= '0';
reg1 <= '0';
reg2 <= '0';
reg3 <= '0';
elsif (rising_edge(clk)) then
reg0 <= '0';
reg1 <= '0';
reg2 <= '0';
reg3 <= '0';
case? addr is
when x"00" =>
reg0 <= '1';
when x"1-" =>
if (addr(3 downto 0) = "0011") then
reg1 <= '1';
else
reg2 <= '1';
end if;
when others =>
reg3 <= '1';
end case?;
end if;
end process;
The second
when in the case above is where I'm having trouble. The compiler will set reg1 to always '0' (which you can check in the RTL viewer). This sort of makes sense to me because since you told the compiler you didn't care about the first 4 bits it just assumed the if would fail and reg1 is hardwired to '0'. However, I'm not entirely convinced this assumption is correct, what I would expect is to always fall into this specific case regardless of the lower 4bits but sill use their actual value inside. For example, if you changed it to
when x"1-" =>
dataout <= addr(3 downto 0)
wouldn't you expect the output to be the same as the 4 lower bits of the address input? Compiling this gives you a dataout stuck at GND (as notified by a warning message or seen in the RTL viewer).
Thank you all for your help!
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May be the tool is saying you made up your mind that you don't care about lower 4 bits then you contradicted that....
Honored Contributor
