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Altera_Forum's avatar
Altera_Forum
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11 years ago

numbers, numbers...

Being new to VHDL, I must admit I find quite confusing the correct application of the use numbers in VHDL. For the problem I wish to have help on in my thread here, I have found that my VHDL si...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Thank you for your response!

Now, this bit you've suggested... 


  elsif falling_edge (IN_CLK) then 
       if falling_edge(IN_E) and IN_CSn='0' and IN_RW='0' then    --Grab data from data bus and program into indexed register.

... I see TWO clock events in the SAME process. I did not think you could do that?! Based on the fact I have tried to do this in the past and just got errors.

Andy