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Altera_Forum
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17 years ago

Node missing source error

I'm having some problems with a schematic design. I'm trying to merge 8 4-bit buses into a 32-bit bus. I've named the buses "nextC[3..0]" etc. and I am feeding them into a bus called "nextC[31..0]".

The error I'm getting is:

"Error: Node "nextC[0]" is missing source"

"Error: Node "nextC[1]" is missing source"

"Error: Node "nextC[2]" is missing source"

.

.

.

"Error: Node "nextC[31]" is missing source"

I don't understand why I'm getting the error. The 4-bit buses are connected to other 4-bit buses.

7 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    I am also getting this error when I connect an 8-bit bus to the 8-bit output of a lpm_ff. The bus is named q[7..0] and is connected using a bus line to q[7..0] of the DFF. This seems coorect yet I get a compiler error "Error: Node "q0" is missing source" for each signal.

    Any help is appreciated.
  • Altera_Forum's avatar
    Altera_Forum
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    --- Quote Start ---

    I'm having some problems with a schematic design. I'm trying to merge 8 4-bit buses into a 32-bit bus. I've named the buses "nextC[3..0]" etc. and I am feeding them into a bus called "nextC[31..0]".

    The error I'm getting is:

    "Error: Node "nextC[0]" is missing source"

    "Error: Node "nextC[1]" is missing source"

    "Error: Node "nextC[2]" is missing source"

    .

    .

    .

    "Error: Node "nextC[31]" is missing source"

    I don't understand why I'm getting the error. The 4-bit buses are connected to other 4-bit buses.

    --- Quote End ---

    Hi,

    can you post your schematic ?
  • Altera_Forum's avatar
    Altera_Forum
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    Did you connect every node of nextC[3..0] with a wire (with the corresponding net name) coming from the original bus?

  • Altera_Forum's avatar
    Altera_Forum
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    I posted the section of the schematic with the errors. Ignore the logic since it's randomly connected after the cutout. The compiler says:

    Warning: No superset bus at connection <---the dest bus

    Warning: Pin "DIN6" not connected

    Warning: Pin "DIN5" not connected

    Warning: Pin "DIN4" not connected

    Warning: Pin "DIN3" not connected

    Warning: Pin "DIN2" not connected

    Warning: Pin "DIN1" not connected

    Warning: Pin "DIN0" not connected

    Warning: Pin "DIN7" not connected

    Error: Node "dest7" is missing source

    Error: Node "dest6" is missing source

    Error: Node "dest5" is missing source

    Error: Node "dest4" is missing source

    Error: Node "dest0" is missing source

    Error: Node "dest1" is missing source

    Error: Node "dest2" is missing source

    Error: Node "dest3" is missing source

    Error: Node "din[7]" is missing source

    Error: Node "din[6]" is missing source

    Error: Node "din[5]" is missing source

    Error: Node "din[4]" is missing source

    Error: Node "din[3]" is missing source

    Error: Node "din[2]" is missing source

    Error: Node "din[1]" is missing source

    Error: Node "din[0]" is missing source

    I've check the drafting and all lines seem properly connected. I tried redrawing, renaming and reconfiguring and it didn't get rid of the errors. Replacing the individual pins for din[7..0] with a singe bus pin did fix the "node din(x) missing source" error.
  • Altera_Forum's avatar
    Altera_Forum
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    Yeah, instead of writing din7, din6 and so on you have to write din[7], din[6], etc. on each wire.

    The same for dest: dest[7], dest[6], etc.

    It will work!

    Cheers

    OD
  • Altera_Forum's avatar
    Altera_Forum
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    That worked!!! Thank you OrchestraDirector. The examples in the Atera help screens don't use brackets and that was my stumbling point.