Hi,
Then may be can try with the preserve or noprune attribute in the second link posted https://www.intel.com/content/www/us/en/docs/programmable/683819/23-4/preserve-for-debug-overview.html
Preserve link https://www.intel.com/content/www/us/en/programmable/quartushelp/17.0/hdl/vhdl/vhdl_file_dir_preserve.htm
Noprune link https://www.intel.com/content/www/us/en/programmable/quartushelp/17.0/hdl/vhdl/vhdl_file_dir_noprune.htm
I had tried with a sample code and I can find the signal in signal-tap check screenshot below:
Code:
entity example_module_vhdl is
port (
a, b : in std_logic
);
end entity example_module_vhdl;
architecture Behavioral of example_module_vhdl is
signal and_result : std_logic;
attribute noprune: boolean;
attribute noprune of and_result: signal is true;
begin
process(a, b)
begin
and_result <= a and b;
end process;
end architecture Behavioral;
Screenshot:
Thanks,
Regards,
Sheng