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Altera_Forum's avatar
Altera_Forum
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18 years ago

No timing path applicable to specified source and destination

I'm trying to achieve a 4ns hold timing on an external output-only data bus and an output-only clock that are both driven from my Cyclone II FPGA. I'm assigning the following th settings in Quartus I...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Probably get rid of the clock name in the From column and just leave the port name in the To column. This is how I usually see it. I thought the clock name would work, but it's definitely not necessary. (If you have multiple registers driving out, then put the name of the register in the From column. I've seen this when the data and OE registers have different Tco requirements.)