Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

No timing path applicable to specified source and destination

I'm trying to achieve a 4ns hold timing on an external output-only data bus and an output-only clock that are both driven from my Cyclone II FPGA. I'm assigning the following th settings in Quartus I...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

FYI: This particular issue has been fixed by inverting the clock signal (good setup and hold could be achieved). I, however, have been completely unsuccessful in affecting the external timing of the Cyclone II using timing assignments.